• - Integration: Block integration, Clocks and Reset, Clock gating, DFT and DFD, Lint, CDC
• - IP Block Development: Reusable, Pipelined, CDC, Lint, DFT, HW-SW partitioning
• - Protocols: AMBA CHI/AXI/AHB/APB, MIPI (DSI, CSI, Slimbus, Soundwire, Unipro, NAND Flash); PCIe; SAS/SATA; SDIO Host/Device/Memory/Combo; I2C, SPI, UART, MDIO

SystemC addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with a set of class libraries created for design and verification. Tessolve customers are applying SystemC for architectural exploration, performance modelling, functional verification, and high-level synthesis.

• - Flexible resources proficient in verification methodologies and tools.
• - Tools for verification productivity
• - Consultancy programs and continuous improvements through Benchmarking.
• - Training on verification strategy and the latest verification methodologies.

• - Multiple Clock and Voltage Domains
• - Mixed signal low speed and high-speed designs
• - Power sensitive designs
• - Embedded processor-based designs
• - Large number of memory types – SRAM, ROM, CAM etc.
• - Complex Analog testing includes SERDES, DDR and A/D, D/A converters
• - Experience in industry standard EDA tools for Memory BIST, ATPG, JTAG etc. from Mentor Graphics, Synopsys and Cadence
• - Post silicon debug on ATE and Bench, demonstrating ownership from silicon architecture through silicon production

• - Experience in most advanced Process nodes down to 5nm.
• - Integration of Analog & Mixed signal SOC
• - Low Power design
• - High Performance design
• - Expertise on all industry standard EDA tools – Synopsys, Mentor, Cadence, Ansys etc.

• - Tools expertise – Synthesis (Synolify Premier/Pro, Altera Tools), PAR & Timing Analysis (Xilinx & Altera Tools), Debug (Chip scope Altera Signal, Logic Analyzer, Oscilloscope, Trace 32)
• - Simulation Tools – Modelsim, NCSIM, Questasim